Method of fabricating a field effect transistor

ABSTRACT

A field effect transistor in which at least one vertically arranged semiconductor column, with a diameter in the nanometer range, is located between a source and a contact and has an annular surround of a gate contact with retention of an insulation gap. A simplified production method is disclosed and the transistor produced thus is embodied such that the semiconductor columns are embedded in a first and a second insulation layer, between which a metal layer, running to the outside as a gate contact, is arranged, the ends of which, extending upwards through the second insulation layer, are partly converted into an insulator, or removed and replaced by an insulation material.

This application is a 371 of PCT/DE03/03673 Oct. 29, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a field effect transistor provided with avertically oriented semiconductor column of a diameter in the nanometerrange (nano-wire) disposed between a source electrode and a drainelectrode and annularly surrounded at an insulating space by a gateelectrode as well as to a method of its fabrication.

2. The Prior Art

Thin layer transistors are known in which semiconductor material isdeposited in a planar arrangement on flexible substrates. However,mechanical stresses on the substrates easily lead to a release of thesemiconductors from the substrate or to other damages and, hence, tofunctional failure.

It has already been proposed to fabricate transistors of the nanometerrange by the formation of ion trace channels by ion bombardment in afoil composite consisting of two plastic foils and an intermediate layerof metal and by sensitizing the ion trace channels for subsequentetching. Semiconductor material is injected into the etched micro-holesby electro deposition or chemical bath precipitation. Source electrodesand drain electrodes are formed by subsequently metalizing the upper andlower surface of the foil compound. The center layer of metal serves asthe gate electrode.

The advantage of the cylindrical and vertical arrangement of thesetransistors is the mechanical robustness since the foil is flexible andextensible. Moreover, the organic foil material is substantially softerthan the inorganic semiconductor material. As a result, occurringbending, shear and compressive forces are almost completely absorbed bythe foil material so that under bending, flexing and tensile forces thecharacteristic curve of the transistor and other electrical parametersremain substantially constant.

Since micro-holes can be fabricated down to 30 nm and filled withsemiconductor material, transistors on the nanometer scale can befabricated without lithography and without any masking technique.

Depending upon the type of precipitation of the semiconductor material,the process leads to polycrystalline semiconductor columns. The rationof length to diameter of the semiconductor columns is also limited bythe required crystal growth within the micro-holes. Overall, the methodof fabricating the transistors is still too complex since hitherto theion bombardment can be carried out only in select scientificenvironments.

OBJECT OF THE INVENTION

It is an object of the invention to provide a field effect transistor ofthe type initially referred to which can be fabricated withmonocrystalline semiconductor columns even without ion irradiation. Asuitable simple and industrially applicable method of its fabrication isto be provided in connection therewith.

SUMMARY OF THE INVENTION

In accordance with the invention, the object is accomplished by thecharacteristics of claims 1 and 2. Useful embodiments are the subject ofthe sub-claims.

In accordance therewith, the semiconductor columns are embedded in afirst and in a second insulating layer between which there is provided ametal layer extending outwardly as a gate electrode. The ends of themetal layer which upwardly extend through the insulating layer arepartially converted to an insulator or partially removed and replaced byan insulating material.

Such a transistor can be fabricated by the following method steps:

-   -   free-standing semiconductor columns are grown vertically on a        conductive substrate;    -   a first insulating layer is deposited on the semiconductor        columns;    -   onto which a first conductive metal layer and a second        insulating layer are deposited thereafter;    -   the resulting laminate is etched planar to the point of removing        the portion of the first metal layer covering the semiconductor        columns;    -   the ends of the metal layer penetrating to the surface of the        laminate are etched back in accordance with their metal and a        third insulating layer is deposited on the laminate whereupon        the laminate is again etched planar;    -   or    -   the ends of the metal layer penetrating to the surface are        converted to an insulator by oxidation or nitriding;    -   finally depositing a second metal layer on the laminate.

Compared to current vertical nano-transistors, the transistor offers thefollowing advantages:

-   -   The structure of the field effect transistor allows for an        extremely high packing density and extremely small dimensions        without any need to apply lithographic processes.    -   The substrates used may be rigid or flexible.    -   Ion beams are not necessarily required for the fabrication.    -   The process makes possible the growth of mono-crystalline        semiconductor columns. Transistors with mono-crystalline        semiconductors have higher switching rates than those with        poly-crystalline semiconductors.

DESCRIPTION OF THE SEVERAL DRAWINGS

The novel features which are considered to be characteristic of theinvention are set forth with particularity in the appended claims. Theinvention itself, however, in respect of its structure, construction andlay-out as well as manufacturing techniques, together with other objectsand advantages thereof, will be best understood from the followingdescription of preferred embodiments when read in connection with theappended drawings, in which:

FIG. 1 depicts the first method step of fabricating a field effecttransistor in accordance with the invention—growing of the free-standingsemiconductor columns on a metallic conductive substrate;

FIG. 2 depicts the second method step—depositing a first insulatinglayer;

FIG. 3 depicts the third and fourth method step—depositing a first meallayer and a second insulating layer;

FIG. 4 depicts the fifth method step—planar etching;

FIGS. 5A-C depicts the sixth method step—insulating the ends of theupwardly penetrating metal layer;

FIG. 6 depicts the seventh method step—depositing a second metal layer,a cross-section of the completed structure of the transistor; and

FIG. 7 depicts a cross-section of an array of transistors which can befabricated in accordance with the method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown in FIG. 1, vertically free-standing semiconductor columns 2 areinitially grown on a conductive substrate 1 which may be flexible orrigid. This may be carried out by an unordered process as known, forinstance, from /1/ in respect of the electro-chemical growth ofZnO-columns. Alternatively, ZnO could be deposited by vaporizing Zn orZnO, see /2/. However, it is also possible so to prepare that in anordered or unordered fashion nuclei are generated from which thecolumnar growth proceeds. Ni-dots, for instance, may be used for growingZnO-columns /2/or Ni-dots may be used for the vertical growth ofC60-nano-tubes, see /3/, Fig. D. Ordered nuclei may be generated bylithographic methods, see /3/or by non-lithographic methods, such as,for instance, dislocation stages of misaligned crystal surfaces. In thecase of non-lithographically fabricated nuclei the size limitationsinherent in lithography do not apply. The columnar growth is solelydetermined by the size of the nucleus. Semiconductor columns may,however, also be produced in etches ion trace channels of polymer films.Free-standing semiconductor columns are also formed after subsequentremoval of the foil material, see /4/.

The semiconductor columns (nano-fibers/nano-tubes) grown on thesubstrates have hitherto gained importance chiefly for the constructionof structural components for electron field emission, luminescencediodes and solar cells with an extremely thin absorption layer.

Aside from the materials mentioned for the semiconductor columns, suchmaterials as GaP, see /5/, InAs, CdTe and others may also be used.

As shown in FIG. 2, an insulating layer 3 is deposited after thesemiconductor columns 2 have been grown. The deposition may be carriedout by spin-coating of a polymer or by vaporization, DVD (chemical vapordeposition) or other known processes of forming an insulating layer,such as, for instance, an oxide or nitride.

The insulating layer 3 also covers the side surfaces of thesemiconductor columns 1. A first conductive metal layer 4, which lateron constitutes the gate electrode of the transistor, is deposited on theinsulating layer 3 by sputtering, vaporization, chemical vapordeposition or a similar process. Thereafter, a further insulating layer5 is deposited (FIG. 3), and the upper layer of the laminate formed inthis manner is etched planar (FIG. 4). This may be done by a horizontalion beam (ion beam etching) or by plasma, chemical or electro-chemicaletching processes of the kind sufficiently known in semiconductortechnology. Thereafter, the upwardly penetrating ends of the metal layer4 are insulated. This may be carried out by etching back the metalprotruding to the surface by a metal-specific etching step (FIG. 5A) andby applying a further insulating layer 10 (FIG. 5B) which is planarizedin turn (FIG. 5C). Alternatively, as shown in FIG. 5C, the metalprotruding to the surface may be converted to an insulator 6 by chemicaloxidizing or nitriding. Finally, a second metal layer 7 is deposited(FIG. 6). This metal layer is electrically connected to thesemiconductor column, and later on it serves as source electrode anddrain electrode.

In the area of the center contact which acts as a gate electrode, achannel 8 is formed at the outside of the semiconductor column 2 which,provided the semiconductor column 2 is sufficiently thin, may extendover the entire thickness of the column.

FIG. 7 depicts an array of transistors. The gate electrode alwayssurrounds the semiconductor column 2 in an annular fashion and is,overall, continuous. All electrodes (source, drain, gate) may becontrolled as an array or they may be divided by lithographic processes.Such arrays may be used in control circuits and displays. In an array,several hundreds of transistors are combined as an optical pixel.

The method allows fabrication of transistors with semiconductor columnsin the range of 10 to 500 nm diameter. The heights of the semiconductorcolumns lie in the same range. At very small diameters, the transistormay be operated in a quantum regime.

LIST OF LITERATURE CITED

-   /1/ Koenenkamp et al.: Thin Film Deposition on Free-standing ZnO    Columns; Appl. Phys. Lett. 77, No. 16 (16 Oct. 2000), pp. 2275-2277.-   /2/ Seung Chu Lyu et al.: Low Temperature Growth of ZnO Nano-wire    Array Using Vapour Deposition Method, Chemistry of Materials, to be    published.-   /3/ Teo et al.: Nanotech Conference, Santiago de Compostela, Sep.    9-13, 2002-10-09.-   /4/ Engelhardt, Koenenkamp: Electrodeposition of Compound    Semiconductors in Polymer Channels of 100 nm Diameter; J. Appl.    Phys., 90, No. 8 (15 Oct. 2002), pp. 4287-4289.-   /5/ Gudiksen/Lieber: Diameter-Selective Semiconductor Nanowires, J.    Am. Chem. Soc. 122 (2000), pp. 8801-8802.

LIST OF REFERENCE CHARACTERS USED

-   -   1 Substrate    -   2 Semiconductor Column    -   3 Insulating Layer    -   4 Metal Layer    -   5 Insulating Layer    -   6 Insulator    -   7 Metal Layer    -   8 Channel

1. A method of fabricating a field effect transistor in which at leastone vertically aligned semiconductor column of a diameter in thenanometer range is present between a source electrode and a drainelectrode and is annularly surrounded by a gate electrode with aninsulating space between them, the method comprising: free-standingsemiconductor columns are grown vertically on a conductive substrate; afirst insulating layer is deposited on the semiconductor columns; afirst conductive metal layer and a second insulating layer are depositedthereon; the developing laminate is etched planar to the point of theportion of the first conductive metal layer covering the semiconductorcolumns is removed again; the end of the first conductive metal layerpenetrating to the surface of the laminate are etched back in ametal-specific manner and a third insulating layer is deposited on thelaminate with subsequent renewed planar etching; or the ends of thefirst conductive metal layer penetrating to the surface of the laminateare converted to an insulator by oxidizing or nitriding; and finallydepositing a second conductive metal layer on the laminate.
 2. Themethod of claim 1, wherein the laminate or individual layers are dividedinto individual arrays by a lithographic process.
 3. The method of claim1, wherein the growing of the semiconductor columns is carried outelectro-chemically.
 4. The method of claim 1, wherein the growing of thesemiconductor columns is carried out by sputtering.
 5. The method ofclaim 1, wherein the growing of the semiconductor columns is carried outby a CVD process.
 6. The method of claim 1, wherein the growing of thesemiconductor columns is carried out by vaporization.
 7. The method ofclaim 1, wherein the growing of the semiconductor columns is carried outin ion trace channels of a polymeric film which is subsequently removed.